SH7785 Datasheet, PDF (190/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Memory Management Unit (MMU)
Bit
31 to 14
13 to 8
7 to 4
3 to 0
Initial
Bit Name Value
R/W
⎯
All 0
R
EPR
ESZ
Undefined R/W
Undefined R/W
⎯
All 0
R
Description
Reserved
For details on reading/writing these bits, see General
Precautions on Handling of Product.
Page Control Information
Each bit has the same function as the corresponding
bit of the unified TLB (UTLB). For details, see section
7.4, TLB Functions (TLB Extended Mode; MMUCR.ME
= 1)
Reserved
For details on reading/writing these bits, see General
Precautions on Handling of Product.
7.2.7 Physical Address Space Control Register (PASCR)
PASCR controls the operation in the physical address space.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0 0 0 0 0 0 0
R/W: R R R R R R R
Bit: 15 14 13 12 11 10 9
Initial value: 0 0 0 0 0 0 0
R/W: R R R R R R R
000000000
RRRRRRRRR
876543210
UB
0 00000000
R R/W R/W R/W R/W R/W R/W R/W R/W
Rev.1.00 Jan. 10, 2008 Page 160 of 1658
REJ09B0261-0100