SH7785 Datasheet, PDF (155/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

6. Floating-Point Unit (FPU)
Section 6 Floating-Point Unit (FPU)
6.1 Features
The FPU has the following features.
• Conforms to IEEE754 standard
• 32 single-precision floating-point registers (can also be referenced as 16 double-precision
registers)
• Two rounding modes: Round to Nearest and Round to Zero
• Two denormalization modes: Flush to Zero and Treat Denormalized Number
• Six exception sources: FPU Error, Invalid Operation, Divide By Zero, Overflow, Underflow,
and Inexact
• Comprehensive instructions: Single-precision, double-precision, graphics support, and system
control
• In the SH-4A, the following three instructions are added on to the instruction set of the SH-4
FSRRA, FSCA, and FPCHG
When the FD bit in SR is set to 1, the FPU cannot be used, and an attempt to execute an FPU
instruction will cause an FPU disable exception (general FPU disable exception or slot FPU
disable exception).
Rev.1.00 Jan. 10, 2008 Page 125 of 1658
REJ09B0261-0100