SH7785 Datasheet, PDF (54/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

1. Overview
1.5 Physical Memory Address Map
The SH7785 supports 32-bit virtual address space, and supports both 29-bit and 32-bit physical
address spaces. For details of mappings from the virtual address space to the physical address
spaces, see section 7, Memory Management Unit (MMU).
Figure 1.4 shows the relationship between the AREASEL bits and the physical memory address
map. The 32-bit physical address space corresponds with the address space of the SuperHyway
bus.
MMSELR
AREASEL[2:0]*
H'0000 0000
H'0400 0000
H'0800 0000
H'0C00 0000
H'1000 0000
H'1400 0000
H'1800 0000
H'1C00 0000
H'2000 0000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7(Reserved)
(Undefined)
H'4000 0000
H'4400 0000
H'4800 0000
H'4C00 0000
H'5000 0000
H'5400 0000
H'5800 0000
H'5C00 0000
H'6000 0000
H'6400 0000
H'6800 0000
H'6C00 0000
H'7000 0000
H'7400 0000
H'7800 0000
H'7C00 0000
H'8000 0000
DDR-SDRAM
(undefined)
H'C000 0000
PCI (PCIC)
H'E000 0000
H'FFFF FFFF ^{(Internal resource)}
B'000 B'001 B'010 B'011 B'100 B'101 B'110
LBSC
LBSC
LBSC
DBSC3
LBSC
LBSC
LBSC
LBSC
LBSC
LBSC
DBSC3
PCIC
LBSC
LBSC
LBSC
LBSC
DBSC2
DBSC3
LBSC
LBSC
LBSC
LBSC
LBSC
DBSC2
DBSC3
PCIC
LBSC
LBSC
LBSC
LBSC
DBSC2
DBSC3
DBSC4
DBSC5
LBSC
LBSC
LBSC
LBSC
LBSC
LBSC
LBSC
LBSC
LBSC
LBSC
LBSC
LBSC
PCIC
LBSC
LBSC
DBSC0
DBSC1
DBSC2
DBSC3
DBSC4
DBSC5
DBSC6
DBSC7
DBSC8
DBSC9
DBSC10
DBSC11
DBSC12
DBSC13
DBSC14
DBSC15
DBSC0
DBSC1
DBSC2
DBSC3
DBSC4
DBSC5
DBSC6
DBSC7
DBSC8
DBSC9
DBSC10
DBSC11
DBSC12
DBSC13
DBSC14
DBSC15
DBSC0
DBSC1
DBSC2
DBSC3
DBSC4
DBSC5
DBSC6
DBSC7
DBSC8
DBSC9
DBSC10
DBSC11
DBSC12
DBSC13
DBSC14
DBSC15
DBSC0
DBSC1
DBSC2
DBSC3
DBSC4
DBSC5
DBSC6
DBSC7
DBSC8
DBSC9
DBSC10
DBSC11
DBSC12
DBSC13
DBSC14
DBSC15
DBSC0
DBSC1
DBSC2
DBSC3
DBSC4
DBSC5
DBSC6
DBSC7
DBSC8
DBSC9
DBSC10
DBSC11
DBSC12
DBSC13
DBSC14
DBSC15
DBSC0
DBSC1
DBSC2
DBSC3
DBSC4
DBSC5
DBSC6
DBSC7
DBSC8
DBSC9
DBSC10
DBSC11
DBSC12
DBSC13
DBSC14
DBSC15
DBSC0
DBSC1
DBSC2
DBSC3
DBSC4
DBSC5
DBSC6
DBSC7
DBSC8
DBSC9
DBSC10
DBSC11
DBSC12
DBSC13
DBSC14
DBSC15
PCIC
PCIC
PCIC
PCIC
PCIC
PCIC
PCIC
Note: Memory Address Map Select Register (MMSELR) Area Select Bit (AREASEL)
For details, refer to section 11.4.1, Memory Address Map Select Register (MMSELR).
29-bit physical
address space
32-bit physical
address space
(extended mode)
Figure 1.4 Relationship between AREASEL Bits and Physical Memory Address Map
Rev.1.00 Jan. 10, 2008 Page 24 of 1658
REJ09B0261-0100