SH7785 Datasheet, PDF (925/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Display Unit (DU)
19.3.31 Plane n Mode Register (PnMR) (n = 1 to 6)
The plane n mode registers (PnMR, n = 1 to 6) set the display operation for plane n.
Bit: 31 30 29 28 27
—————
Initial value: 0
0
0
0
0
R/W: R R R R R
Internal update:
Bit: 15 14 13 12 11
—
PnSPIM
—
Initial value: 0
0
0
0
0
R/W: R R/W R/W R/W R
Internal update:
OO O
26 25 24 23 22 21 20 19
— — — — — — PnYCDF —
0
0
0
0
0
0
0
0
R R R R R R R/W R
O
10 9
8
7
6
5
4
3
—
PnCPSL PnDC —
PnBM
—
0
0
0
0
0
0
0
0
R R/W R/W R/W R R/W R/W R
OOO
OO
18 17 16
— PnTC PnWAE
0
0
0
R R/W R/W
OO
2
1
0
—
PnDDF
0
0
0
R R/W R/W
OO
Bit
Bit Name
31 to 21 ⎯
Initial
Value
All 0
20
PnYCDF 0
19, 18 ⎯
All 0
17
PnTC
0
16
PnWAE 0
15
⎯
0
Internal
R/W Update Description
R
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Yes
Plane n YC Data Format
0: Sets the order of YC data to UYVY format.
1: Sets the order of YC data to YUYV format.
R
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Yes
Plane n Transparent Color
0: When set to 8 bits/pixel display, the
transparent color is the color set in the plane
n transparent color 1 register (PnTC1R)
1: When set to 8 bits/pixel display, any of the
transparent colors set in CP1TR to CP4TR
can be a transparent color
CP1TR to CP4TR to be used are determined
by the setting of the PnCPSL bit.
R/W Yes
Plane n Wrap Around Enable
0: Wraparound is not performed for plane n
1: Wraparound is performed for plane n
R
⎯
Reserved
This bit is always read as 0. The write value
should always be 0.
Rev.1.00 Jan. 10, 2008 Page 895 of 1658
REJ09B0261-0100