SH7785 Datasheet, PDF (1513/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

29. User Break Controller (UBC)
With the above settings, the user break occurs after executing the instruction at address
H'00037226 where ASID is H'80 and before executing the instruction at address H'0003722E
where ASID is H'70.
• Example 1-5
Register settings: CBR0 = H'00000013 / CRR0 = H'00002001 / CAR0 = H'00000500 /
CAMR0 = H'00000000 / CBR1 = H'00000813 / CRR1 = H'00002001 / CAR1 = H'00001000 /
CAMR1 = H'00000000 / CDR1 = H'00000000 / CDMR1 = H'00000000 / CETR1 =
H'00000005 / CBCR = H'00000000
Specified conditions: Independent for channels 0 and 1
⎯ Channel 0
Address: H'00000500 / Address mask: H'00000000
Bus cycle: Instruction fetch (before executing the instruction)
ASID is not included in the conditions.
⎯ Channel 1
Address: H'00001000 / Address mask: H'00000000
Data: H'00000000 / Data mask: H'00000000 / Execution count: H'00000005
Bus cycle: Instruction fetch (before executing the instruction)
Execution count: 5
ASID and data values are not included in the conditions.
With the above settings, the user break occurs for channel 0 before executing the instruction at
address H'00000500. The user break occurs for channel 1 after executing the instruction at
address H'00001000 four times; before executing the instruction five times.
• Example 1-6
Register settings: CBR0 = H'40800013 / CRR0 = H'00002003 / CAR0 = H'00008404 /
CAMR0 = H'00000FFF / CBR1 = H'40700013 / CRR1 = H'00002001 / CAR1 = H'00008010 /
CAMR1 = H'00000006 / CDR1 = H'00000000 / CDMR1 = H'00000000 / CETR1 =
H'00000000 / CBCR = H'00000000
Specified conditions: Independent for channels 0 and 1
⎯ Channel 0
Address: H'00008404 / Address mask: H'00000FFF / ASID: H'80
Bus cycle: Instruction fetch (after executing the instruction)
Rev.1.00 Jan. 10, 2008 Page 1483 of 1658
REJ09B0261-0100