SH7785 Datasheet, PDF (199/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Memory Management Unit (MMU)
Figure 7.10 shows a flowchart of a memory access using the ITLB.
VA is
in P4 area
Instruction access to virtual address (VA)
VA is
in P2 area
VA is
in P1 area
0
CCR.ICE?
1
VA is in P0, U0,
or P3 area
MMUCR.AT = 1
No
Yes
Hardware ITLB
miss handling
Search UTLB
Yes
Record in ITLB
Match?
No
Instruction TLB
miss exception
Instruction TLB protection
violation exception
No
SH = 0
and (MMUCR.SV = 0 or
SR.MD = 0)
No
VPNs match
and V = 1
Yes
Yes
No
VPNs match,
ASIDs match, and
V=1
Yes
No
Only one
entry matches
Yes
Instruction TLB
multiple hit exception
0 (User)
0
PR?
1
SR.MD?
1 (Privileged)
No
C=1
and CCR.ICE = 1
Yes
Internal resource access
Memory access
(Non-cacheable)
Cache access
Figure 7.10 Flowchart of Memory Access Using ITLB (TLB Compatible Mode)
Rev.1.00 Jan. 10, 2008 Page 169 of 1658
REJ09B0261-0100