SH7785 Datasheet, PDF (1361/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

26. Serial Sound Interface (SSI) Module
26.4.6 Receive Operation
As with transmission the reception can be controlled in one of two ways: either DMA or an
interrupt driven.
Figures 26.23 and 26.24 show the flow of operation.
When disabling the SSI module, the SSI clock must be supplied continuously until the module
enters in the idle state, which is indicated by the IIRQ bit.
Note: * SCKD = 0: Clock input through the SSI_SCK pin
SCKD = 1: Clock input through the SSI_CLK pin
Rev.1.00 Jan. 10, 2008 Page 1331 of 1658
REJ09B0261-0100