SH7785 Datasheet, PDF (497/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. DDR2-SDRAM Interface (DBSC2)
Table 12.3 Positions of Valid Data for Access with Burst Length of 4, when the External
Data Bus Width Is Set to 32 Bits
(1) Little Endian First Access
Byte access
(address 8n +
0,1,2,3)
Invalid
Byte access
(address 8n +
4,5,6,7)
Valid
Word access
Invalid
(address 8n + 0,2)
Word access
Valid
(address 8n + 4,6)
Longword access Invalid
(address 8n + 0)
Longword access Valid
(address 8n + 4)
Quadword access Valid
(address 8n + 0)
Second Access Third Access
Valid
Invalid
Fourth Access
Invalid
Invalid
Invalid
Invalid
Valid
Invalid
Valid
Invalid
Valid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
(2) Big Endian First Access
Byte access
(address 8n +
0,1,2,3)
Valid
Byte access
(address 8n +
4,5,6,7)
Invalid
Word access
Valid
(address 8n + 0,2)
Word access
Invalid
(address 8n + 4,6)
Longword access Valid
(address 8n + 0)
Longword access Invalid
(address 8n + 4)
Quadword access Valid
(address 8n + 0)
Second Access Third Access
Invalid
Invalid
Fourth Access
Invalid
Valid
Invalid
Invalid
Invalid
Valid
Invalid
Valid
Valid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Rev.1.00 Jan. 10, 2008 Page 467 of 1658
REJ09B0261-0100