SH7785 Datasheet, PDF (802/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Watchdog Timer and Reset (WDT)
16.4.4 Time until WDT Counters Overflow
The relationship between WDTCNT and WDTBCNT is shown in figure 16.2. The example shown
in the figure is the operation in interval timer mode, where WDTCNT restarts counting after it has
overflowed. In watchdog timer mode, WDTCNT and WDTBCNT are cleared to 0 after the reset
state is exited and start counting up again.
WDTCNT value
WDTST
Cleared to 0
on overflow
Incremented on each
WDTBCNT overflow
H'0000 0000
WDTBCNT value
H'0003 FFFF
Incremented every
peripheral clock (Pck)
cycle
Cleared to 0
on overflow
Time
H'0000 0000
TME
WOVF
IOVF
Counting starts
Flag is set
Time
Figure 16.2 WDT Counting Operations (Example in Interval Timer Mode)
Rev.1.00 Jan. 10, 2008 Page 772 of 1658
REJ09B0261-0100