SH7785 Datasheet, PDF (696/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
Figure 14.1 shows a block diagram of the DMAC.
On-chip
memory
On-chip
peripheral
module
Peripheral
bus controller
DMA transfer request signal
DMA transfer end signal
Interrupt controller
DMINT0 to DMINT11
DMAE0
DMAE1
DREQ0 to DREQ3
DRAK0 to DRAK3
DACK0 to DACK3
External ROM
External RAM
External I/O
LBSC
DDRIF
PCIC
DMAC channels 0 to 5
Iteration
control
Register
control
Start-up
control
Request
priority
control
Bus
interface
SAR0 to SAR5
DAR0 to DAR5
TCR0 to TCR5
CHCR0 to CHCR5
DMAOR0
DMARS0 to DMARS2
SARB0 to SARB3
DARB0 to DARB3
TCRB0 to TCRB3
DMAC channels 6 to 11
Iteration
control
Register
control
Start-up
control
Request
priority
control
Bus
interface
SAR6 to SAR11
DAR6 to DAR11
TCR6 to TCR11
CHCR6 to CHCR11
DMAOR1
DMARS3 to DMARS5
SARB6 to SARB9
DARB6 to DARB9
TCRB6 to TCRB9
Legend:
SAR0 to SAR11:
SARB0 to SARB3, SARB6 to SARB11:
DAR0 to DAR11:
DARB0 to DARB3, DARB6 to DARB9:
TCR0 to TCR11:
TCRB0 to TCRB3, TCRB6 to TCRB9:
CHCR0 to CHCR11:
DMAOR0 and DMAOR1:
DMARS0 to DMARS5:
DMINT0 to DMINT11:
DMAE0:
DMAE1:
DMA source address register
DMA source address register B
DMA destination address register
DMA destination address register B
DMA transfer count register
DMA transfer count register B
DMA channel control register
DMA operation register
DMA extended resource register
DMA transfer end/half-end interrupt request*
channels 0 to 5 address error interrupt request
channels 6 to 11 address error interrupt request
Note: * The half-end interrupt request is valid for only channels 0 to 3 and channels 6 to 9.
Figure 14.1 Block Diagram of DMAC
Rev.1.00 Jan. 10, 2008 Page 666 of 1658
REJ09B0261-0100