SH7785 Datasheet, PDF (1083/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

21. Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
4
RE
0
R/W Receive Enable
Enables or disables the start of serial reception by the
SCIF.
Serial reception is started when a start bit or a
synchronization clock input is detected in
asynchronous mode or clocked synchronous mode,
respectively, while the RE bit is set to 1.
It should be noted that clearing the RE bit to 0 does not
affect the ER, BRK, FER, PER, RDF, and DR flags in
SCFSR, and ORER flag in SCLSR, which retain their
states.
Serial reception begins once the start bit is detected in
these states.
0: Reception disabled
1: Reception enabled*³
3
REIE
0
R/W Receive Error Interrupt Enable
Enables or disables generation of receive-error
interrupt (ERI) and break interrupt (BRI) requests. The
REIE bit setting is valid only when the RIE bit is 0.
Receive-error interrupt (ERI) and break interrupt (BRI)
requests can be cleared by reading 1 from ER and
BRK in SCFSR, or the ORER flag in SCLSR, then
clearing the flag to 0, or by clearing the RIE and REIE
bits to 0. When REIE is set to 1, ERI and BRI interrupt
requests are generated even if RIE is cleared to 0. In
DMA transfer, this setting is made if the interrupt
controller is to be notified of ERI and BRI interrupt
requests.
0: Receive-error interrupt (ERI) and break interrupt
(BRI) requests disabled
1: Receive-error interrupt (ERI) and break interrupt
(BRI) requests enabled
2
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev.1.00 Jan. 10, 2008 Page 1053 of 1658
REJ09B0261-0100