SH7785 Datasheet, PDF (537/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. DDR2-SDRAM Interface (DBSC2)
12.4.13 DDRPAD DIC, ODT, OCD Setting Register (DBDICODTOCD)
The SDRAM refresh status register (DBRFSTS) is a readable/writable register. It is initialized
only upon power-on reset.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
⎯
⎯
⎯
⎯
⎯
⎯
⎯ DDRSIG ⎯
⎯
⎯
⎯ DIC_AD DIC_DQ DIC_CK DIC
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R/W R R R R R/W R/W R/W R/W
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
⎯
⎯
⎯
ODTEN1 ODTEN0
ODT_
EARLY
T_ODT1 T_ODT0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
R/W: R R R R/W R/W R/W R/W R/W R R R R R R/W R/W R/W
Bit
Bit Name
31 to 25 ⎯
Initial
Value
All 0
24
DDRSIG 0
23 to 20 ⎯
All 0
19
DIC_AD 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
R/W Write Preamble Time Setting Bit
Sets the preamble time of the DQS signal to be output
when data is written to the DDR2-SDRAM. The number
of cycles is the number of DDR clock cycles.
0: Write preamble time = 0.5 cycle
1: Write preamble time = 1 cycle
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
R/W Address and Command Pin Impedance Value
This bit should be set to the same value as the value set
for DIC of EMRS(1) in the DDR2-SDRAM.
0: Normal
1: Weak
Rev.1.00 Jan. 10, 2008 Page 507 of 1658
REJ09B0261-0100