SH7785 Datasheet, PDF (321/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Interrupt Controller (INTC)
(8) Interrupt Mask Clear Register 0 (INTMSKCLR0)
INTMSKCLR0 is a 32-bit write-only register that clears the mask settings for each of the interrupt
requests IRQn (n = 0 to 7). Undefined values are read from this register.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IC00 IC01 IC02 IC03 IC04 IC05 IC06 IC07 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit
Name
31
IC00
30
IC01
29
IC02
28
IC03
27
IC04
26
IC05
25
IC06
24
IC07
23 to 0 —
Initial
Value
0
0
0
0
0
0
0
0
All 0
R/W Description
R/W Clears masking of IRQ0
interrupt.
R/W Clears masking of IRQ1
interrupt.
R/W Clears masking of IRQ2
interrupt.
R/W Clears masking of IRQ3
interrupt.
R/W Clears masking of IRQ4
interrupt.
[When read]
Undefined values are
read.
[When written]
0: No effect
1: Clears the
corresponding interrupt
mask (enables the
interrupt)
R/W Clears masking of IRQ5
interrupt.
R/W Clears masking of IRQ6
interrupt.
R/W Clears masking of IRQ7
interrupt.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev.1.00 Jan. 10, 2008 Page 291 of 1658
REJ09B0261-0100