SH7785 Datasheet, PDF (236/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Memory Management Unit (MMU)
(5) CCR.CB
The CB bit in CCR is invalid. Whether a cacheable write for the P1 area is performed in copy-
back mode or write-though mode is determined by the WT bit in the PMB.
(6) IRMCR.MT
The MT bit in IRMCR is valid for a memory-mapped PMB write.
(7) QACR0, QACR1
AREA0[4:2]/AREA1[4:2] fields of QACR0/QACR1 are extended to AREA0[7:2]/AREA1[7:2]
corresponding to physical address [31:26].
(8) LSA0, LSA1, LDA0, LDA1
L0SADR, L1SADR, L0DADR, and L1DADR fields are extended to bits 31 to 10.
When using 32-bit address mode, the following notes should be applied to software.
1. For the SE bit switching, switching from 0 to 1 is only supported in a boot routine which is
allocated in an area where caching and TLB-based address translation are not allowed and runs
after a power-on reset or manual reset.
2. After switching the SE bit, an area in which the program is allocated becomes the target of the
PMB address translation. Therefore, the area should be recorded in the PMB before switching
the SE bit. An address which may be accessed in the P1 or P2 area such as the exception
handler should also be recorded in the PMB.
3. When an external memory access occurs by an operand memory access located before the
MOV.L instruction which switches the SE bit, external memory space addresses accessed in
both address modes should be the same.
4. Note that the V bit is mapped to both address array and data array in PMB registration. That is,
first write 0 to the V bit in one of arrays and then write 1 to the V bit in another array.
Rev.1.00 Jan. 10, 2008 Page 206 of 1658
REJ09B0261-0100