SH7785 Datasheet, PDF (1042/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. Graphics Data Translation Accelerator (GDTA)
20.3.35 MC Future Frame V Pointer Register (MCFVPR)
MCFVPR is in the MC register block and specifies the V pointer address for a future frame.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MC_FVPT
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MC_FVPT
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 0 MC_FVPT All 0
R/W Future Frame V Pointer
The address should be set. 0 should be written to bits 2
to 0.
Note: An 8-byte boundary address must be specified.
Rev.1.00 Jan. 10, 2008 Page 1012 of 1658
REJ09B0261-0100