SH7785 Datasheet, PDF (1620/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

32. Electrical Characteristics
CLKOUT
A25 to A0
CSn
RD/WR
RD
D31 to D0
(Read)
WEn
BS
T1
T2
t_AD
t_CSD
t_AD
t_CSD
t_RWD
t_RWD
t_RSD
t_RSD
t_RSD
t_RDS
t_WED1
t_WEDF
t_RDH
t_WED1
t_BSD
t_BSD
RDY
t_DACD
DACKn
(SA: IO ← memory)
DACKn
(DA)
t_DACD
t_DACD tDACD
t_DACD
T1
Tw
T2
t_AD
t_CSD
t_AD
t_CSD
t_RWD
t_RWD
t_RSD
t_RSD
t_WED1
t_WEDF
t_RDS
t_RSD
t_RDH
t_WED1
t_BSD
t_BSD
t_RDYS
t_DACD
t_DACD
t_RDYH
t_DACD
t_DACD
t_DACD
T1
Tw
Twe
T2
t_AD
t_CSD
t_AD
t_CSD
t_RWD
t_RWD
t_RSD
t_RSD
t_WED1
t_WEDF
t_RDS
t_RSD
t_RDH
t_WED1
t_BSD
t_BSD
t_RDYS
t_RDYH
t_DACD
t_RDYS
t_DACD
t_RDYH
t_DACD
t_DACD
t_DACD
(1) Basic read cycle (no wait)
Legend:
IO: DACK device
SA: Single-address DMA transfer
DA: Dual-address DMA transfer
Note: DACK is configured as active-high.
(2) Basic read cycle (one internal wait cycle) (3) Basic read cycle (one internal wait + one external wait cycles)
Figure 32.24 Memory Byte Control SRAM Bus Cycle
Rev.1.00 Jan. 10, 2008 Page 1590 of 1658
REJ09B0261-0100