SH7785 Datasheet, PDF (261/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Caches
the dirty bit to 0. This operation is only executable in privileged mode, and an address error
exception occurs in user mode. TLB-related exceptions do not occur.
Do not execute this instruction to invalidate the memory-mapped array areas and control
register areas for which Rn[31:24] is not H'F4, and their reserved areas (H'F0 to H'F3, H'F5 to
H'FF).
8.5.2 Prefetch Operation
This LSI supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a
cache miss. If it is known that a cache miss will result from a read or write operation, it is possible
to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss
due to the read or write operation, and so improve software performance. If a prefetch instruction
is executed for data already held in the cache, or if the prefetch address results in a UTLB miss or
a protection violation, the result is no operation, and an exception is not generated. Details of the
prefetch instruction are given in section 11, Instruction Descriptions of the SH-4A Extended
Functions Software Manual.
• Prefetch instruction (OC)
• Prefetch instruction (IC)
: PREF @Rn
: PREFI @Rn
Rev.1.00 Jan. 10, 2008 Page 231 of 1658
REJ09B0261-0100