SH7785 Datasheet, PDF (177/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Memory Management Unit (MMU)
256
H'0000 0000
P0 area
Cacheable
Address translation possible
Physical ²⁵⁶
address space
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
U0 area
Cacheable
Address translation possible
Area 7
H'0000 0000
H'8000 0000
P1 area
Cacheable
H'A000 0000 ^{Address translation not possible}
P2 area
Non-cacheable
Address translation not possible
H'C000 0000
P3 area
Cacheable
H'E000 0000 ^{Address translation possible}
P4 area
Non-cacheable
H'FFFF FFFF ^{Address translation not possible}
Privileged mode
Address error
Store queue area
Address error
On-chip memory area
Address error
User mode
H'8000 0000
H'E000 0000
H'E400 0000
H'E500 0000
H'E600 0000
H'FFFF FFFF
Figure 7.3 Virtual Address Space (AT in MMUCR = 1)
(a) P0, P3, and U0 Areas
The P0, P3, and U0 areas allow address translation using the TLB and access using the cache.
When the MMU is disabled, replacing the upper 3 bits of an address with 0s gives the
corresponding physical address. Whether or not the cache is used is determined by the CCR
setting. When the cache is used, switching between the copy-back method and the write-
through method for write accesses is specified by the WT bit in CCR.
When the MMU is enabled, these areas can be mapped onto any physical address space in 1-,
4-, 64-Kbyte, or 1-Mbyte page units in TLB compatible mode and in 1-, 4-, 8-, 64, 256-Kbyte,
1-, 4-, or 64-Mbyte page units in TLB extended mode using the TLB. When CCR is in the
cache enabled state and the C bit for the corresponding page of the TLB entry is 1, accesses
can be performed using the cache. When the cache is used, switching between the copy-back
method and the write-through method for write accesses is specified by the WT bit of the TLB
entry.
When the P0, P3, and U0 areas are mapped onto the control register area which is allocated in
the area 7 in physical address space by means of the TLB, the C bit for the corresponding page
must be cleared to 0.
Rev.1.00 Jan. 10, 2008 Page 147 of 1658
REJ09B0261-0100