SH7785 Datasheet, PDF (210/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Memory Management Unit (MMU)
MMUCR
Entry specification
LRUI
−
URB
−
URC
SV ME
−
TI − AT
SQMD
PTEH
PTEL
PTEA
VPN
−
ASID
−
PPN
− V − C D SH WT
−
EPR
ESZ
−
Entry 0
Entry 1
Entry 2
ASID[7:0] VPN[31:10] V
ASID[7:0] VPN[31:10] V
ASID[7:0] VPN[31:10] V
Write
PPN[28:10] ESZ[3:0] SH C EPR[5:0] D WT
PPN[28:10] ESZ[3:0] SH C EPR[5:0] D WT
PPN[28:10] ESZ[3:0] SH C EPR[5:0] D WT
Entry 63 ASID[7:0] VPN[31:10] V
PPN[28:10] ESZ[3:0] SH C EPR[5:0] D WT
Figure 7.17 Operation of LDTLB Instruction (TLB Extended Mode)
7.5.4 Hardware ITLB Miss Handling
In an instruction access, this LSI searches the ITLB. If it cannot find the necessary address
translation information (ITLB miss occurred), the UTLB is searched by hardware, and if the
necessary address translation information is present, it is recorded in the ITLB. This procedure is
known as hardware ITLB miss handling. If the necessary address translation information is not
found in the UTLB search, an instruction TLB miss exception is generated and processing passes
to software.
Rev.1.00 Jan. 10, 2008 Page 180 of 1658
REJ09B0261-0100