SH7785 Datasheet, PDF (395/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Local Bus State Controller (LBSC)
Bit
2 to 0
Initial
Bit Name Value R/W
AREASEL 000
R/W
Description
DDR2-SDRAM/PCI Memory Space Select
000: Sets area 3 (H'0C00 0000 to H'0FFF FFFF) as the
DDR2-SDRAM space and the other areas as the
local bus space
001: Sets area 3 (H'0C00 0000 to H'0FFF FFFF) as the
DDR2-SDRAM space, area 4 (H'1000 0000 to
H'13FF FFFF) as the PCI space, and the other
areas as the local bus space
010: Sets areas 2 and 3 (H'0800 0000 to H'0FFF FFFF)
as the DDR2-SDRAM space and the other areas
as the local bus space
011: Sets areas 2 and 3 (H'0800 0000 to H'0FFF FFFF)
as the DDR2-SDRAM space, area 4 (H'1000 0000
to H'13FF FFFF) as the PCI space, and the other
areas as the local bus space
100: Sets areas 2 to 5 (H'0800 0000 to H'17FF FFFF)
as the DDR-SDRAM space
101: Sets areas 2 to 5 (H'0800 0000 to H'17FF FFFF)
as the local bus space
110: Sets area 4 (H'1000 0000 to H'13FF FFFF) as the
PCI space, and the other areas as the local bus
space
111: Setting prohibited
This register should be written by the CPU. Before writing to this register, set that no access will
be generated from the DMAC, GDTA, DU or PCIC and execute the SYNCO instruction
immediately before the MOV instruction to write this register, etc. to prevent remaining
unprocessed access.
Also, execute following instructions immediately after the MOV instruction to write to this
register.
1. MOV instruction to read this register
2. MOV instruction to read this register
3. SYNCO instruction
Rev.1.00 Jan. 10, 2008 Page 365 of 1658
REJ09B0261-0100