SH7785 Datasheet, PDF (529/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. DDR2-SDRAM Interface (DBSC2)
12.4.8 SDRAM Refresh Control Register 0 (DBRFCNT0)
The SDRAM refresh control register 0 (DBRFCNT0) is a readable/writable register. It is
initialized only upon power-on reset.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ARFEN
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R/W
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SRFEN
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R/W
Bit
Bit Name
31 to 17 ⎯
Initial
Value
All 0
16
ARFEN 0
15 to 1 ⎯
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
R/W Auto-Refresh Enable Bit
Enables or disables automatic issue of auto-refresh.
The auto-refresh command is issued periodically
according to the settings of DBRFCNT1/2.
For details on the auto-refresh command issue timing,
refer to section 12.5.5, Auto-Refresh Operation.
0: Disables automatic issue of auto-refresh.
1: Enables automatic issue of auto-refresh.
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
Rev.1.00 Jan. 10, 2008 Page 499 of 1658
REJ09B0261-0100