SH7785 Datasheet, PDF (240/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Memory Management Unit (MMU)
Notes: 1. An exception handling routine is an entire set of instructions that are executed from the
address (VBR + offset) upon occurrence of an exception to the RTE for returning to the
original program or to the RTE delay slot.
2. MMU-related exceptions are: instruction TLB miss exception, instruction TLB miss
protection violation exception, data TLB miss exception, data TLB protection violation
exception, and initial page write exception.
3. Instruction accesses include the PREFI and ICBI instructions.
Rev.1.00 Jan. 10, 2008 Page 210 of 1658
REJ09B0261-0100