SH7785 Datasheet, PDF (1082/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

21. Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
6
RIE
0
R/W Receive Interrupt Enable*¹
Enables or disables generation of a receive-data-full
interrupt (RXI) request when the RDF flag or DR flag in
SCFSR is set to 1, a receive-error interrupt (ERI)
request when the ER flag in SCFSR is set to 1, and a
break interrupt (BRI) request when the BRK flag in
SCFSR or the ORER flag in SCLSR is set to 1.
0: Receive-data-full interrupt (RXI) request, receive-
error interrupt (ERI) request, and break interrupt
(BRI) request disabled
1: Receive-data-full interrupt (RXI) request, receive-
error interrupt (ERI) request, and break interrupt
(BRI) request enabled
5
TE
0
R/W Transmit Enable
Enables or disables the start of serial transmission by
the SCIF.
Serial transmission is started when transmit data is
written to SCFTDR while the TE bit is set to 1.
0: Transmission disabled
1: Transmission enabled*²
Rev.1.00 Jan. 10, 2008 Page 1052 of 1658
REJ09B0261-0100