SH7785 Datasheet, PDF (149/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

5. Exception Handling
(14) FPU Exception
• Source: Exception due to execution of a floating-point operation
• Transition address: VBR + H'00000100
• Transition operations:
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR . The R15 contents at this time are saved in SGR. Exception code H'120 is set in
EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR +
H'0100.
FPU_exception()
{
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = H'0000 0120;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'0000 0100;
}
Rev.1.00 Jan. 10, 2008 Page 119 of 1658
REJ09B0261-0100