SH7785 Datasheet, PDF (1535/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

30. User Debugging Interface (H-UDI)
30.4.2 TAP Control
Figure 30.3 shows the internal states of the TAP controller. The controller supports the state
transitions specified in JTAG with the subset.
• The condition of transition is the TMS value at the rising edge of TCK.
• The TDI value is sampled at the rising edge of TCK and shifted at the falling edge of TCK.
• The TDO value is changed at the falling edge of TCK. The TDO is in the high impedance state
other than in the Shift-DR or Shift-IR state.
• When TRST is changed to 0, the transition to the Test-Logic-Reset state is performed
asynchronously with the TCK signal.
1 Test -Logic-Reset
0
1
0 Run-Test/Idle
1
Select-DR-Scan
0
1
Capture-DR
0
Shift-DR 0
1
1
Exit1-DR
0
Pause-DR 0
1
0
Exit2-DR
1
Update-DR
1
0
1
Select-IR-Scan
0
1
Capture-IR
0
Shift-IR
0
1
1
Exit1-IR
0
Pause-IR 0
1
0
Exit2-IR
1
Update-IR
1
0
Figure 30.3 Diagram of Transitions of TAP Controller State
Rev.1.00 Jan. 10, 2008 Page 1505 of 1658
REJ09B0261-0100