SH7785 Datasheet, PDF (1130/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. Serial I/O with FIFO (SIOF)
Figure 22.1 shows a block diagram of the SIOF.
SIOF interrupt
request
Bus interface
Peripheral bus
Control
registers
Transmit
FIFO
(32 bits ×
16 stages)
Receive
FIFO
(32 bits ×
16 stages)
Transmit
Receive
Pck
control data
control data
Baud rate ^1/nMCLK _{Timing control}
generator
P/S
SIOF_MCLK
SIOF_SCK SIOF_SYNC
SIOF_TXD
Figure 22.1 Block Diagram of SIOF
S/P
SIOF_RXD
Rev.1.00 Jan. 10, 2008 Page 1100 of 1658
REJ09B0261-0100