SH7785 Datasheet, PDF (87/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Instruction
MULU.W Rm,Rn
NEG
NEGC
SUB
SUBC
SUBV
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Operation
Unsigned,
Rn × Rm → MACL
16 × 16 → 32 bits
0 – Rm → Rn
0 – Rm – T → Rn,
borrow → T
Rn – Rm → Rn
Rn – Rm – T → Rn,
borrow → T
Rn – Rm → Rn,
underflow → T
3. Instruction Set
Instruction Code
Privileged T Bit
0010nnnnmmmm1110 —
—
New
—
0110nnnnmmmm1011 —
0110nnnnmmmm1010 —
0011nnnnmmmm1000 —
0011nnnnmmmm1010 —
0011nnnnmmmm1011 —
—
—
Borrow
—
—
—
Borrow
—
Underflow —
Table 3.6 Logic Operation Instructions
Instruction
AND Rm,Rn
AND #imm,R0
AND.B #imm, @(R0,GBR)
NOT Rm,Rn
OR Rm,Rn
OR #imm,R0
OR.B #imm, @(R0,GBR)
TAS.B @Rn
TST Rm,Rn
TST #imm,R0
TST.B #imm, @(R0,GBR)
XOR Rm,Rn
Operation
Rn & Rm → Rn
R0 & imm → R0
(R0 + GBR) & imm
→ (R0 + GBR)
~Rm → Rn
Rn | Rm → Rn
R0 | imm → R0
(R0 + GBR) | imm
→ (R0 + GBR)
When (Rn) = 0, 1 → T
Otherwise, 0 → T
In both cases,
1 → MSB of (Rn)
Rn & Rm;
when result = 0, 1 → T
Otherwise, 0 → T
R0 & imm;
when result = 0, 1 → T
Otherwise, 0 → T
(R0 + GBR) & imm;
when result = 0, 1 → T
Otherwise, 0 → T
Rn ∧ Rm → Rn
Instruction Code
Privileged T Bit
0010nnnnmmmm1001 —
—
11001001iiiiiiii —
—
11001101iiiiiiii —
—
New
—
—
—
0110nnnnmmmm0111 —
0010nnnnmmmm1011 —
11001011iiiiiiii —
11001111iiiiiiii —
—
—
—
—
—
—
—
—
0100nnnn00011011 —
Test —
result
0010nnnnmmmm1000 —
11001000iiiiiiii —
11001100iiiiiiii —
0010nnnnmmmm1010 —
Test —
result
Test —
result
Test —
result
—
—
Rev.1.00 Jan. 10, 2008 Page 57 of 1658
REJ09B0261-0100