SH7785 Datasheet, PDF (95/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 4 Pipelining
4. Pipelining
This LSI is a 2-ILP (instruction-level-parallelism) superscalar pipelining microprocessor.
Instruction execution is pipelined, and two instructions can be executed in parallel.
4.1 Pipelines
Figure 4.1 shows the basic pipelines. Normally, a pipeline consists of eight stages: instruction
fetch (I1/I2/I3), decode and register read (ID), execution (E1/E2/E3), and write-back (WB). An
instruction is executed as a combination of basic pipelines.
1. General Pipeline
I1
-Instruction fetch
I2
I3
-Predecode
2. General Load/Store Pipeline
I1
I2
-Instruction fetch
I3
-Predecode
3. Special Pipeline
I1
I2
I3
-Instruction fetch
-Predecode
4. Special Load/Store Pipeline
I1
I2
-Instruction fetch
I3
-Predecode
ID
-Instruction
decode
-Issue
-Register read
E1
-Forwarding
ID
-Instruction
decode
-Issue
-Register read
E1
-Address
calculation
ID
-Instruction
decode
-Issue
-Register read
E1
-Forwarding
ID
E1
-Instruction
decode
-Issue
-Register read
E2
E3
-Operation
E2
E3
-Memory data access
E2
E3
-Operation
E2
E3
WB
-Write-back
WB
-Write-back
WB
-Write-back
WB
5. Floating-Point Pipeline
I1
I2
-Instruction fetch
I3
-Predecode
ID
-Instruction
decode
-Issue
FS1
FS2
-Register read -Operation
-Forwarding
FS3
-Operation
FS4
-Operation
FS
-Operation
-Write-back
6. Floating-Point Extended Pipeline
I1
I2
I3
ID
FE1
FE2
FE3
FE4
FE5
FE6
FS
-Instruction fetch
-Predecode -Instruction -Register read -Operation -Operation -Operation -Operation -Operation -Operation
decode -Forwarding
-Write-back
-Issue
Figure 4.1 Basic Pipelines
Rev.1.00 Jan. 10, 2008 Page 65 of 1658
REJ09B0261-0100