SH7785 Datasheet, PDF (1362/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

26. Serial Sound Interface (SSI) Module
(1) Reception Using DMA Controller
Start
Release reset,
specify configuration bits
in SSICR
Setup DMA controller to transfer data
from SSI module to memory
Enable SSI module,
enable DMA,
enable error interrupts
Wait for interrupt from DMAC or SSI
Specify TRMD, EN, SCKD,
SWSD, MUEN, DEL, PDTA,
SDTA, SPDP, SWSP, SCKP,
SWL, DWL, CHNL
EN = 1,
DMEN = 1,
UIEN = 1, OIEN = 1
SSI
Yes
Error interrupt?
No
No
Has DMAC Rx data
been completed?
Yes
Yes
More data
to be received?
No
Disable SSI module,
disable DMA
disable error interrupt,
enable Idle interrupt
Wait for idle interrupt
from SSI module
End*
EN = 0,
DMEN = 0
UIEN = 0, OIEN = 0,
IIEN = 1
Note: * When SSI error interrupt occurs (underflow/overflow), back to start
and execute flow again.
Figure 26.23 Reception Using DMA Controller
Rev.1.00 Jan. 10, 2008 Page 1332 of 1658
REJ09B0261-0100