SH7785 Datasheet, PDF (1384/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

27. NAND Flash Memory Controller (FLCTL)
27.3.8 Interrupt DMA Control Register (FLINTDMACR)
FLINTDMACR is a 32-bit readable/writable register that enables or disables DMA transfer
requests or interrupts. A transfer request from the FLCTL to the DMAC is issued after each access
mode has started.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOTRG[1:0]
AC1
CLR
AC0 DREQ1 DREQ0
CLR EN EN
Initial value: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10
Initial value: 0
0
0
0
0
0
R/W: R R R R R R
9
8
7
6
5
4
3
2
1
0
STE BTO TRR TRR STER RBER TE TR TR
RB ERB EQF1 EQF0 INTE INTE INTE INTE1 INTE0
0
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev.1.00 Jan. 10, 2008 Page 1354 of 1658
REJ09B0261-0100