SH7785 Datasheet, PDF (1029/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. Graphics Data Translation Accelerator (GDTA)
20.3.20 CL Palette Pointer Register (CLPLPR)
CLPLPR is in the CL register block and sets the color conversion table pointer. The RAM 0
address used for a work area should be specified. This register setting is used only in the ARBG
conversion mode, not used in the YUYV conversion mode.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CL_PLPT
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CL_PLPT
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name
Value R/W Description
31 to 0 CL_PLPT
All 0 R/W Palette Pointer Setting
An address in the range from H'FE41_0000 to
H'FE41_1FFF (P4 area address) should be specified.
Note: A 4-byte boundary address must be specified.
Rev.1.00 Jan. 10, 2008 Page 999 of 1658
REJ09B0261-0100