SH7785 Datasheet, PDF (1065/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

21. Serial Communication Interface with FIFO (SCIF)
Figure 21.1 shows a block diagram of the SCIF. Figures 21.2 to 21.6 show block diagrams of the
I/O ports in the SCIF. There are six channels in this LSI. In figures 21.2 to 21.6, the channel
number is omitted.
Module data bus
SCFRDRn (128 stages)
(64 stages)
SCFTDRn (128 stages)
(64 stages)
SCIFn_RXD
SCRSRn
SCTSRn
SCIFn_TXD
SCIFn_SCK
Parity generation
Parity check
SCSMRn
SCLSRn
SCTFDRn
SCRFDRn
SCFCRn
SCFSRn
SCSCRn
SCSPTRn
SCRERn
Transmission/
reception control
SCBRRn
Baud rate generator
Clock
External clock
SCIF0_CTS
SCIF0_RTS
SCIF
Legend:
SCRSRn:
SCFRDRn:
SCTSRn:
SCFTDRn:
SCSMRn:
SCSCRn:
SCFSRn:
SCBRRn:
SCSPTRn:
SCFCRn:
SCTFDRn:
SCRFDRn:
SCLSRn:
SCRERn:
Receive shift register
Receive FIFO data register
Transmit shift register
Transmit FIFO data register
Serial mode register
Serial control register
Serial status register
Bit rate register
Serial port register
FIFO control register
Transmit FIFO data count register
Receive FIFO data count register
Line status register
Serial error register
Note: n = 0 to 5
Channels 1 to 5 do not have SCIF1_CTS to SCIF5_CTS and SCIF1_RTS to SCIF5_RTS.
Figure 21.1 Block Diagram of SCIF
Figures 21.2 to 21.6 show block diagrams of the I/O ports in SCIF.
Pck
Pck/4
Pck/16
Pck/64
TXIn
RXIn
ERIn
BRIn
Rev.1.00 Jan. 10, 2008 Page 1035 of 1658
REJ09B0261-0100