SH7785 Datasheet, PDF (756/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
CLKOUT
Bus cycle
DREQ
(Overrun 0, High level)
DRAK (High-active)
CPU
1st acceptance
DMAC
2nd acceptance
DACK (High-active)
Acceptance started
Accepted after one cycle of CLKOUT
at the falling edge of DACK
CLKOUT
Bus cycle
DREQ
(Overrun 1, High level)
DRAK (High-active)
CPU
1st acceptance
DMAC
2nd acceptance
DACK (High-active)
: Non-sensitive period
Acceptance started
Accepted after one cycle of CLKOUT
at the rising edge of DACK
Figure 14.20 Example 1 of DREQ Input Detection in Burst Mode Level Detection (Byte
Transfer in 8/16/32/64-Bit Bus Width, Word Transfer in 16/32/64-Bit Bus Width, or
Longword Transfer in 32/64-Bit Bus Width)
Rev.1.00 Jan. 10, 2008 Page 726 of 1658
REJ09B0261-0100