SH7785 Datasheet, PDF (1156/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. Serial I/O with FIFO (SIOF)
22.3.13 Control Data Assign Register (SICDAR)
SICDAR is a 16-bit readable/writable register that specifies the position of the control data in a
frame. SICDAR can be specified only when the FL bits in SIMDR are set to 1xxx (x: don't care.).
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CD0E — — —
CD0A[3:0]
CD1E — — —
CD1A[3:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R R R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
15
CD0E
0
R/W
14 to 12 ⎯
All 0 R
11 to 8 CD0A[3:0] 0000 R/W
7
CD1E
0
R/W
6 to 4 ⎯
All 0 R
Description
Control Channel 0 Data Enable
0: Disables transmission and reception of control
channel 0 data
1: Enables transmission and reception of control
channel 0 data
Reserved
These bits are always read as 0. The write value should
always be 0.
Control Channel 0 Data Assigns 3 to 0
These bits specify the position of control channel 0 data
in a receive or transmit frame as B'0000 (0) to B'1110
(14).
1111: Setting prohibited
• Transmit data for the control channel 0 data is
specified in the SITD0 bit in SITCR.
• Receive data for the control channel 0 data is stored
in the SIRD0 bit in SIRCR.
Control Channel 1 Data Enable
0: Disables transmission and reception of control
channel 1 data
1: Enables transmission and reception of control
channel 1 data
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev.1.00 Jan. 10, 2008 Page 1126 of 1658
REJ09B0261-0100