SH7785 Datasheet, PDF (767/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Clock Pulse Generator (CPG)
15.3 Clock Operating Modes
Table 15.2 shows the relationship between setting of the mode pins (MODE0 to MODE4) and the
clock operating modes.
Table 15.2 Clock Operating Modes and Operations of the Oscillator and PLLs
Clock
Operating
Mode
Setting of Mode Control Pins*¹*²
MODE4 MODE3 MODE2 MODE1 MODE0
Divider 1 PLL1
PLL2
0
L
L
L
L
L
×1
On (× 72) On
1
L
L
L
L
H
×1
On (× 72) On
2
L
L
L
H
L
×1
On (× 72) On
3
L
L
L
H
H
×1
On (× 72) On
16
H
L
L
L
L
×1
On (× 36) On
17
H
L
L
L
H
×1
On (× 36) On
18
H
L
L
H
L
×1
On (× 36) On
19
H
L
L
H
H
×1
On (× 36) On
Notes: 1. For the MODE0 to MODE4 pins, setting except the above mode pins (MODE0 to
MODE4) is prohibited.
2. L stands for 'low level', and H stands for 'high level'.
Rev.1.00 Jan. 10, 2008 Page 737 of 1658
REJ09B0261-0100