SH7785 Datasheet, PDF (1360/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

26. Serial Sound Interface (SSI) Module
(2) Transmission using Interrupt Data Flow Control
Start
Release reset,
specify configuration bits
in SSICR
Enable SSI module,
enable DMA,
enable error interrupts
n = ( (CHNL + 1) x 2)
Loop
Wait for interrupt from SSI
Data interrupt?
Yes
Load data of channel n
Next Channel
Specify TRMD, EN, SCKD,
SWSD, MUEN, DEL, PDTA,
SDTA, SPDP, SWSP, SCKP,
SWL, DWL, CHNL
EN = 1,
DIEN = 1,
UIEN = 1, OIEN = 1
No
Use SSI status register bits
to realign data
after underflow/overflow
Yes
More data
to be send?
No
Disable SSI module,
disable DMA
disable error interrupt,
enable Idle interrupt
Wait for Idle interrupt
from SSI module
EN = 0,
DIEN = 0
UIEN = 0, OIEN = 0,
IIEN = 1
End
Figure 26.22 Transmission Using Interrupt Data Flow Control
Rev.1.00 Jan. 10, 2008 Page 1330 of 1658
REJ09B0261-0100