SH7785 Datasheet, PDF (743/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
(2) Bus Modes
Bus modes include cycle steal mode and burst mode. The modes are chosen by the TB and LCKN
bits in CHCR.
(a) Cycle Steal Mode
• Normal mode 1 (CHCR.LCKN = 0, CHCR.TB = 0)
In cycle steal normal mode 1, the DMAC gives the SuperHyway bus mastership to another bus
master after a one-transfer unit (byte, word, longword, 16-byte, or 32-byte unit). When the
next transfer is requested, the DMAC issues the next transfer request, another transfer is
performed for one-transfer unit. When the transfer ends, the DMAC gives bus mastership to
the other bus master. This is repeated until the transfer end conditions are satisfied.
Cycle steal normal mode 1 can be set for only channels 0 to 5.
Figure 14.6 shows an example of DMA transfer timing in cycle steal normal mode 1.
DREQ
Bus mastership returned to CPU once
SuperHyway
bus cycle
CPU
CPU
CPU
DMAC DMAC
Read/Write
CPU
DMAC DMAC
Read/Write
CPU
Figure 14.6 DMA Transfer Timing Example in Cycle Steal Normal Mode 1
(DREQ Low Level Detection)
• Normal mode 2 (CHCR.LCKN = 1, CHCR.TB = 0)
In cycle steal normal mode 2, the DMAC does not keep the SuperHyway bus mastership, and
obtains the bus mastership in every transfer unit of read or write cycle.
Figure 14.7 shows an example of DMA transfer timing in cycle steal normal mode 2.
DREQ
Bus mastership returned to CPU once
SuperHyway
bus cycle
CPU
CPU
CPU
DMAC CPU
Read
DMAC CPU
Write
DMAC CPU
Read
DMAC CPU
Write
Figure 14.7 DMA Transfer Timing Example in Cycle Steal Normal Mode 2
(DREQ Low Level Detection)
Rev.1.00 Jan. 10, 2008 Page 713 of 1658
REJ09B0261-0100