SH7785 Datasheet, PDF (486/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Local Bus State Controller (LBSC)
Table 11.22 Register Settings for Divided-Up DACKn Output in DMA1 Transfer in Write
Access Using the MPX Interface
Not Divided
Divided
Bus Width
Bus Cycle
IW1 and IW0 in
[Bit]
Access Size Number IWW in CSnBCR CSnWCR
IWW in CSnBCR
32
Byte
1
⎯
⎯
Undividable
Word
1
⎯
⎯
Undividable
Longword 1
⎯
⎯
Undividable
16 bytes
4
B'000
B'11 to B'01
B'111 to B'001
32 bytes
1
⎯
⎯
Undividable
64
Byte
1
⎯
⎯
Undividable
Word
1
⎯
⎯
Undividable
Longword 1
⎯
⎯
Undividable
16 bytes
4
B'000
B'11 to B'01
B'111 to B'001
32 bytes
1
⎯
⎯
Undividable
Note: "⎯" means an arbitrary setting value. When transfer is done in a single bus cycle, DACKn
is not divided up because DACKn is output once in DMA1 transfer.
Rev.1.00 Jan. 10, 2008 Page 456 of 1658
REJ09B0261-0100