SH7785 Datasheet, PDF (851/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Display Unit (DU)
Pin Name
Number I/O
Function
Signal Name Used
in This Section
DG5
1
Output Digital green 5
DB0
1
Output Digital blue 0
DB1
1
Output Digital blue 1
DB2
1
Output Digital blue 2
DB3
1
Output Digital blue 3
DB4
1
Output Digital blue 4
DB5
1
Output Digital blue 5
Note: In this section, unless otherwise noted, "dot clock" refers to the output dot clock.
19.3 Register Descriptions
Register update methods include external update and internal update.
(1) External Update
An "external update" is an update which reflects the address-mapped register settings made by the
CPU after the end of CPU access. Registers related to display control (for example, the display
system control register) and the settings of which are updated through external updates can be
overwritten during the vertical blanking interval without display flicker by using the VBK flag and
FRM flag in the display status register (DSSR) indicating the start position of the vertical blanking
interval.
(2) Internal Update
An "internal update" is an update which reflects the address-mapped register settings with the
internal update timing of the display unit (DU). Hence in the case of a register with an internal
update function, even when the CPU overwrites address-mapped registers related to display
operation without being aware of the display timing, display flicker can be prevented.
An internal update is performed during the interval in which the DRES bit in the display system
control register (DSYSR) is 1 and at the beginning of each frame. The internal update performed
at the beginning of each frame can be disabled using the IUPD bit in DSYSR.
Internal updates are performed on the following bits by setting to 1 the DRES bit in DSYSR:
Rev.1.00 Jan. 10, 2008 Page 821 of 1658
REJ09B0261-0100