SH7785 Datasheet, PDF (1178/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. Serial I/O with FIFO (SIOF)
(4) 16-bit Stereo Data (1)
L/R method, rising edge sampling, slot No.0 used for left-channel data, slot No.1 used for right-
channel data, and frame length = 32 bits
1 frame
SIOF_SCK
SIOF_SYNC
SIOF_TXD
SIOF_RXD
L-channel data
Slot No.0
No bit delay
R-channel data
Slot No.1
Specifications: TRMD[1:0] = 11,
TDLE = 1,
RDLE = 1,
CD0E = 0,
REDG = 1,
TDLA[3:0] = 0000,
RDLA[3:0] = 0000,
CD0A[3:0] = 0000,
FL[3:0] = 1101 (frame length: 32 bits)
TDRE = 1,
TDRA[3:0] = 0001,
RDRE = 1,
RDRA[3:0] = 0001,
CD1E = 0,
CD1A[3:0] = 0000
Figure 22.16 Transmit and Receive Timing (16-Bit Stereo Data (1))
(5) 16-bit Stereo Data (2)
L/R method, rising edge sampling, slot No.0 used for left-channel transmit data, slot No.1 used for
left-channel receive data, slot No.2 used for right-channel transmit data, slot No.3 used for right-
channel receive data, and frame length = 64 bits
SIOF_SCK
SIOF_SYNC
SIOF_TXD
L-channel data
1 frame
R-channel data
SIOF_RXD
Slot No.0
No bit delay
L-channel data
Slot No.1
Slot No.2
R-channel data
Slot No.3
Specifications: TRMD[1:0] = 11, REDG = 1,
FL[3:0] = 1101 (frame length: 64 bits),
TDLE = 1,
TDLA[3:0] = 0000, TDRE = 1,
TDRA[3:0] = 0010,
RDLE = 1,
RDLA[3:0] = 0001, RDRE = 1, RDRA[3:0] = 0011,
CD0E = 0,
CD0A[3:0] = 0000, CD1E = 0,
CD1A[3:0] = 0000
Figure 22.17 Transmit and Receive Timing (16-Bit Stereo Data (2))
Rev.1.00 Jan. 10, 2008 Page 1148 of 1658
REJ09B0261-0100