SH7785 Datasheet, PDF (772/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Clock Pulse Generator (CPG)
15.4.2 Frequency Control Register 1 (FRQCR1)
FRQCR1 is a 32-bit readable/writable register that can select the division ratio of divider 2 for the
CPU clock (lck), the SuperHyway clock (SHck), the peripheral clock (Pck), the DDR clock
(DDRck), the bus clock (Bck), the GDTA clock (GAck), the DU clock (DUck), and the RAM
clock (Uck). To check the division ratio of divider 2 for each clock, read FRQMR1. FRQCR1 can
only be accessed in longwords.
FRQCR1 only changes the division ratio of a clock to which a value other than H'0 has been
written. Therefore, set a value other than H'0 in the bit corresponding to the clock for which you
want to change the division ratio. Other bits should be set to H'0.
To change the division ratio of each clock to the value set in FRQCR1, you must set 1 in the
FRQE bit in FRQCR0 to execute the sequence that changes the frequency. After the sequence is
executed, this register is automatically cleared to H'0000 0000.
However, when changing the division ratio of the DDR clock (DDRck), switch SDRAM to the
self-refreshing state. For details on how to switch to or release the self-refreshing state, see section
12, DDR2-SDRAM Interface (DBSC2).
FRQCR1 is initialized by only a power-on reset via the PRESET pin or a WDT overflow.
BIt:
Initial value:
R/W:
31
IFC3
0
R/W
30
IFC2
0
R/W
29
IFC1
0
R/W
28 27 26 25 24 23 22 21 20 19 18 17 16
IFC0 UFC3 UFC2 UFC1 UFC0 SFC3 SFC2 SFC1 SFC0 BFC3 BFC2 BFC1 BFC0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MFC3 MFC2 MFC1 MFC0 S2FC3 S2FC2 S2FC1 S2FC0 S3FC3 S3FC2 S3FC1 S3FC0 PFC3 PFC2 PFC1 PFC0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev.1.00 Jan. 10, 2008 Page 742 of 1658
REJ09B0261-0100