SH7785 Datasheet, PDF (1665/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix
Reset
Pin Name
(LSI level)
Pin Name
Related
Power
Module Bus
(Module level) Module I/O -on Manual Sleep Standby Release
GNT3/
GNT3
PCIC O PZ K
K
⎯
K
MMCCLK *³
MMCCLK
MMCIF O PZ K
K
K
K
Port E0
GPIO I/O PZ K
K
⎯
K
GNT[2:1] *³
GNT[2:1]
PCIC O PZ K
K
⎯
K
Port E1-E2 GPIO I/O PZ K
K
⎯
K
REQ0/REQOUT*³ REQ0/
PCIC I/O PZ K
K
⎯
K
REQOUT
REQ3*³
Port Q2
GPIO I/O PZ K
K
⎯
K
REQ3
PCIC I PZ K
K
⎯
K
Port E3
GPIO I/O PZ K
K
⎯
K
REQ[2:1] *³
REQ[2:1]
PCIC I PZ K
K
⎯
K
Port E4-E5 GPIO I/O PZ K
K
⎯
K
DEVSEL/
DEVSEL
PCIC I/O PZ K
K
⎯
K
DCLKOUT*³
DCLKOUT DU
O PZ K
K
⎯
K
Port P5
GPIO I/O PZ K
K
⎯
K
PCIFRAME/
PCIFRAME PCIC
I/O PZ
K
K
⎯
K
VSYNC*³
VSYNC
DU
I/O PZ K
K
⎯
K
Port P0
GPIO I/O PZ K
K
⎯
K
IDSEL
INTA*³
IDSEL
INTA
PCIC I I
I
K
⎯
I
PCIC I/O PZ K
K
⎯
K
Port Q4
GPIO I/O PZ K
K
⎯
K
IRDY/HSYNC*³ IRDY
PCIC I/O PZ K
K
⎯
K
HSYNC
DU
I/O PZ K
K
⎯
K
Port P1
GPIO I/O PZ K
K
⎯
K
LOCK/ODDF*³ LOCK
PCIC I/O PZ K
K
⎯
K
ODDF
DU
I/O PZ K
K
⎯
K
Port P3
GPIO I/O PZ K
K
⎯
K
PAR
PAR
PCIC I/O PZ O
K
⎯
O
PCICLK/
DCLKIN*⁴
PCICLK
PCIC I I
PI
K
⎯
K
DCLKIN
DU
II
PI
K
⎯
K
Rev.1.00 Jan. 10, 2008 Page 1635 of 1658
REJ09B0261-0100