SH7785 Datasheet, PDF (638/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. PCI Controller (PCIC)
Bit
11
10 to 4
3
2
1
0
Bit Name
MBTOI
⎯
TAI
MAI
RDPEI
WDPEI
Initial
Value
0
All 0
0
0
0
0
R/W
Description
SH: R/WC Master Bus Time-Out Interrupt
PCI: R
An interrupt is detected when IRDY is not asserted
within 8 clock cycles during data transfer.
0: A master bus timeout interrupt was not generated
1: A master bus timeout interrupt was generated
SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.
SH: R/WC Target-Abort Interrupt
PCI: R
Indicates that a transaction was terminated by a target
abort when a device other than the PCIC is a bus
master.
0: A target abort interrupt was not generated
1: A target abort interrupt was generated
SH: R/WC Master-Abort Interrupt
PCI: R
Indicates that a transaction was terminated by a
master abort when a device other than the PCIC is a
bus master.
0: A master abort interrupt was not generated
1: A master abort interrupt was generated
SH: R/WC Read Parity Error Interrupt
PCI: R
PERR assertion was detected during data read when
a device other than the PCIC is a bus master.
0: A read parity error interrupt was not generated
1: A read parity error interrupt was generated
SH: R/WC Write Parity Error Interrupt
PCI: R
PERR assertion was detected during data write when
a device other than the PCIC is a bus master.
0: A write data parity error interrupt was not generated
1: A write data parity error interrupt was generated
Rev.1.00 Jan. 10, 2008 Page 608 of 1658
REJ09B0261-0100