SH7785 Datasheet, PDF (545/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. DDR2-SDRAM Interface (DBSC2)
command to be issued at time 2 from the following request queue. From the search results it is
seen that advance precharge processing can be executed for the third read (8-byte) request and the
fourth read (16-byte) request. Because the DBSC2 gives priority to preceding requests, it decides
to perform advance precharge processing for the third read (8-byte) request, and issues a PRE
command to the SDRAM.
When the time advances to time 3, the ACT command cannot be issued for the first read (16-byte)
request at time 3 either, and so a search of the following queue is performed for a command which
can be issued. Due to timing constraints, the ACT command cannot be issued for the third read (8-
byte) request, and as a result, issuance of the PRE command corresponding to the fourth read (16-
byte) request is selected.
At time 4, it is possible to execute request processing for the first read (16-byte) request, and an
ACT command is issued to the DDR2-SDRAM.
Thereafter, the processing described above is repeated.
Request
No. Request
Bank to be
accessed
Page state
during request
Time
Time
Time
Time
Time
Time
Time
Time
Time
Time
Time
Time
Time
Time
Time
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
1 Read (16 bytes) Bank 0 Miss
PRE
ACT
READ
2 Read (32 bytes) Bank 1 Hit
READ
READ
3 Read (8 bytes) Bank 2 Miss
PRE
ACT
READ
4 Read (16 bytes) Bank 3 Miss
PRE
ACT
READ
SDRAM command
PRE PRE PRE ACT
ACT READ ACT READ
READ
READ
READ
As the burst length is 4 in the DDR2-SDRAM, the interval between READ commands is always two cycles.
Figure 12.6 Example of Preceding Precharge/Activate Processing
Rev.1.00 Jan. 10, 2008 Page 515 of 1658
REJ09B0261-0100