SH7785 Datasheet, PDF (892/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Display Unit (DU)
19.3.8 Display Unit Extensional Function Enable Register (DEFR)
The display unit extensional function enable register (DEFR) enables extension functions.
DEFR should be set during display reset (the DRES bit and DEN bit in DSYSR should be set to 1
and to 0 respectively) for external updates. If update is performed during display, the display may
flicker.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Internal update:
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — — — — — DCKE ABRE — — — DSAE
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R/W R/W R R R R/W
Internal update:
Bit
31 to 6
Bit Name
⎯
Initial
Value
All 0
5
DCKE
0
Internal
R/W Update Description
R
⎯
Reserved
These bits are always read as undefined. The
write value should always be 0.
R/W None
Input Dot Clock Select Enable
0: The DCLKSEL bit and bit 4 of the FRQSEL
bits in the external sync control register
(ESCR) are disabled.
1: The DCLKSEL bit and bit 4 of the FRQSEL
bits in ESCR are enabled.
The following functions can be used.
• The clock from the DCLKIN pin and the DU
clock (DUck) can be selected as the input
dot clock. Selection is performed using the
DCLKSEL bit in ESCR.
• The dot clock frequency division ratio can be
selected in the range 0 to 32. The frequency
division ratio is set using the FRQSEL bits in
ESCR.
Rev.1.00 Jan. 10, 2008 Page 862 of 1658
REJ09B0261-0100