SH7785 Datasheet, PDF (319/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Bit
Name
15
IM115
14
IM114
13
IM113
12
IM112
11
IM111
10
IM110
9
IM109
8
IM108
7
IM107
6
IM106
5
IM105
4
IM104
3
IM103
10. Interrupt Controller (INTC)
Initial
Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Masks the interrupt source
of IRL7 to IRL4 = LLLL
(H'0).
Masks the interrupt source
of IRL7 to IRL4 = LLLH
(H'1).
Masks the interrupt source
of IRL7 to IRL4 = LLHL
(H'2).
[When read]
0: The interrupt is
accepted.
1: The interrupt is
masked.
[When written]
0: No effect
1: Masks the interrupt
Masks the interrupt source
of IRL7 to IRL4 = LLHH
(H'3).
Masks the interrupt source
of IRL7 to IRL4 = LHLL
(H'4).
Masks the interrupt source
of IRL7 to IRL4 = LHLH
(H'5).
Masks the interrupt source
of IRL7 to IRL4 = LHHL
(H'6).
Masks the interrupt source
of IRL7 to IRL4 = LHHH
(H'7).
Masks the interrupt source
of IRL7 to IRL4 = HLLL
(H'8).
Masks the interrupt source
of IRL7 to IRL4 = HLLH
(H'9).
Masks the interrupt source
of IRL7 to IRL4 = HLHL
(H'A).
Masks the interrupt source
of IRL7 to IRL4 = HLHH
(H'B).
Masks the interrupt source
of IRL7 to IRL4 = HHLL
(H'C).
Rev.1.00 Jan. 10, 2008 Page 289 of 1658
REJ09B0261-0100