SH7785 Datasheet, PDF (1175/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. Serial I/O with FIFO (SIOF)
(2) Regarding Transmit and Receive Classification
The transmit sources and receive sources are signals indicating the state; after being set, if the state
changes, they are automatically cleared by the SIOF.
When the DMA transfer is used, a DMA transfer request is pulled low for one cycle at the end of
DMA transfer.
(3) Processing when Errors Occur
On occurrence of each of the errors indicated as a status in SISTR, the SIOF performs the
following operations.
• Transmit FIFO underflow (TFUDF)
The immediately preceding transmit data is again transmitted.
• Transmit FIFO overflow (TFOVF)
The contents of the transmit FIFO are protected, and the write operation causing the overflow
is ignored.
• Receive FIFO overflow (RFOVF)
Data causing the overflow is discarded and lost.
• Receive FIFO underflow (RFUDF)
An undefined value is output on the bus.
• Frame synchronization error (FSERR)
The internal counter is reset according to the signal in which an error occurs.
• Slot assign error (SAERR)
⎯ If the same slot is assigned to both serial data and control data, the slot is assigned to serial
data.
⎯ If the same slot is assigned to two control data items, the data cannot be transferred
correctly.
Rev.1.00 Jan. 10, 2008 Page 1145 of 1658
REJ09B0261-0100