SH7785 Datasheet, PDF(770/1692 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer

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SH7785 Datasheet, PDF (770/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

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15. Clock Pulse Generator (CPG)

Table 15.6 Register State in Each Processing Mode

Register Name

Abbreviation

Power-on Reset

by the PRESET

Pin, WDT, or

H-UDI

Manual Reset by

WDT or

Multiple

Exception

Sleep or Deep

Sleep

by Sleep

Instruction

Frequency control register 0 FRQCR0

H'0000 0000

Retained

Retained

Frequency control register 1

Frequency display register 1

FRQCR1

FRQMR1

H'0000 0000

H'1xxx xxxx*2

Retained

Retained

Retained

Retained

Sleep control register

SLPCR

H'0000 0000

Retained

Retained

PLL control register

PLLCR

H'0000 0000

Retained

Retained

Standby control register 0*1 MSTPCR0

H'0000 0000

Retained

Retained

Standby control register 1*1 MSTPCR1

H'0000 0000

Retained

Retained

Standby display register*1

MSTPMR

H'00x0 0000*3

Retained

Retained

Notes: 1. For details on the standby control registers, see section 17, Power-Down Mode.

2. The state of this register depends on the settings of mode pins MODE0 to MODE4,

MODE11, and MODE12 obtained on a power-on reset via the PRESET pin. See Table

15.3 or 15.4.

3. The state of this register depends on the setting of mode pins MODE11 and MODE12

obtained on a power-on reset via the PRESET pin.

Rev.1.00 Jan. 10, 2008 Page 740 of 1658

REJ09B0261-0100

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