SH7785 Datasheet, PDF (189/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Bit
7
6 to 3
2
1
0
7. Memory Management Unit (MMU)
Initial
Bit Name Value
ME
0
⎯
All 0
TI
0
⎯
0
AT
0
R/W Description
R/W TLB Extended Mode Switching
0: TLB compatible mode
1: TLB extended mode
For modifying the ME bit value, always set the TI bit to
1 to invalidate the contents of ITLB and UTLB. The
selection of TLB operating mode made by the ME bit
does not affect the functionality or operation of the
PMB.
R
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
R/W TLB Invalidate Bit
Writing 1 to this bit invalidates (clears to 0) all valid
UTLB/ITLB bits. This bit is always read as 0.
R
Reserved
For details on reading from or writing to this bit, see
description in General Precautions on Handling of
Product.
R/W Address Translation Enable Bit
These bits enable or disable the MMU.
0: MMU disabled
1: MMU enabled
MMU exceptions are not generated when the AT bit is
0. In the case of software that does not use the MMU,
the AT bit should be cleared to 0.
7.2.6 Page Table Entry Assistance Register (PTEA)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
−
−
EPR
ESZ
−
−
−
−
Initial value: 0
0
−
−
−
−
−
−
−
−
−
−
0
0
0
0
R/W: R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R
Rev.1.00 Jan. 10, 2008 Page 159 of 1658
REJ09B0261-0100