SH7785 Datasheet, PDF (1386/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

27. NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value
18
AC0CLR 0
17
DREQ1EN 0
16
DREQ0EN 0
15 to 9 —
All 0
8
STERB 0
R/W
R/W
R/W
R/W
R
R/W
Description
FLDTFIFO Clear
Clears the address counter of FLDTFIFO.
0: Retains the address counter value of FLDTFIFO. In
flash-memory access, clear this bit to 0.
1: Clears the address counter of FLDTFIFO. After
clearing the counter, clear this bit to 0
FLECFIFODMA Request Enable
Enables or disables the DMA transfer request issued
from FLECFIFO.
0: Disables the issue of DMA transfer request from
FLECFIFO
1: Enables the issue of DMA transfer request from
FLECFIFO
FLDTFIFODMA Request Enable
Enables or disables the DMA transfer request issued
from FLDTFIFO.
0: Disables the issue of DMA transfer request from
FLDTFIFO
1: Enables the issue of DMA transfer request from
FLDTFIFO
Reserved
These bits are always read as 0. The write value should
always be 0.
Status Error
Indicates the result of status read. This bit is set to 1 if
the specific bit in bits STAT7 to STAT0 in FLBSYCNT is
set to 1 in status read.
Since this bit is a flag bit, 1 cannot be written to this bit.
Only 0 can be written to clear the flag.
0: Indicates that no status error occurs (the specific bit
in bits STAT7 to STAT0 in FLBSYCNT is 0.)
1: Indicates that a status error occurs
For details on the specific bit, see section 27.4.4, Status
Read.
Rev.1.00 Jan. 10, 2008 Page 1356 of 1658
REJ09B0261-0100